Description
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
CVSS breakdown
CVSS 3.1
Attack Vector
Local
Attack Complexity
Low
Privileges Required
High
User Interaction
None
Scope
Changed
Confidentiality
High
Integrity
High
Availability
None
Affected products
- Arm / C1-Premium0 – 0
- Arm / C1-Ultra0 – 0
- Arm / Cortex-A7100 – 0
- Arm / Cortex-X20 – 0
- Arm / Cortex-X30 – 0
- Arm / Cortex-X40 – 0
- Arm / Cortex-X9250 – 0
- Arm / Neoverse N20 – 0
- Arm / Neoverse-V20 – 0
- Arm / Neoverse V30 – 0
- Arm / Neoverse V3AE0 – 0